Current progress of the decompiler

[xvilka]

As you all probably know - we have two students, heavily working on the implementing ESIL -> SSA lifter/converter. As soon this is an important part of the decompiling process, we're getting closer to support simplest possible decompilation process in some graph representation, which should be later converted to the pseudocode (or the C code).

All the development happening in the https://github.com/radare/radeco
Main language of the development - Rust, since it is fast enough, still provides high-level API for our superheavy math.

Whole radeco framework will take the disassembly and the ESIL input from the radare2 and convert it to the pseudocode. Of course it will provide the API to make the changes for the every step of the decompilation, thus interactivity support.

It is using its own IL - RadecoIL, which is not yet documented, presented only in the code, but when we though about its features and specifications, we've read all academic papers about other ILs (like REIL, RREIL, VEX, MAIL, etc). So we're just picking the best things from the all competitors, to not repeat their mistakes.

You can read more information from our students reports on the our blog: http://radare.today

P.S. Yes, since the main output of the radeco will be the ESIL, this means that decompiler would have support for all architectures, which already have ESIL convertors, not only x86/arm/mips, like 8051 e.g.